Work In Progress
it is planned that ESPL1000 should get an AVR Backend and be able to generate
assembly code in the AVR Instructions Set
AVR Instruction Set Manual
AVR Instruction Set (Wikipedia)
The AVR Instruction Set is a RISC Instruction Set.
The Chips (currently being produced by
are reasonably inexpensive and easy to come by.
Variety of good open source emulators available.
The Registers are only 8 bit wide.
Developing a Compiler Backend requires some tooling to test the generated machine code.
I have come across a variety of good Simulators for the AVR Architecture.
Memory Layout Used
- [ ] 3-Address-Code Generation
- [ ] Optimizations on the 3-Address-Code
- [ ] Control Flow Graph with Basic Blocks
- [ ] Register Allocation
- [ ] ...